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?2005 silicon storage technology, inc. s71061-11-000 9/05 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. ssf is a trademark of silicon storage technology, inc. these specifications are subject to change without notice. data sheet 1 mbit (128k x8) page-write eeprom sst29ee010 / sst29ve010 features: ? single voltage read and write operations ? 4.5-5.5v for sst29ee010 ? 2.7-3.6v for sst29ve010 superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention low power consumption ? active current: 20 ma (typical) for 5v and 10 ma (typical) for 2.7v ? standby current: 10 a (typical) fast page-write operation ? 128 bytes per page, 1024 pages ? page-write cycle: 5 ms (typical) ? complete memory rewrite: 5 sec (typical) ? effective byte-write cycle time: 39 s (typical) fast read access time ? 4.5-5.5v operation: 70 and 90 ns ? 2.7-3.6v operation: 150 and 200 ns latched address and data automatic write timing ? internal v pp generation end of write detection ? toggle bit ? data# polling hardware and software data protection product identification can be accessed via software operation ttl i/o compatibility jedec standard ? flash eeprom pinouts and command sets packages available ? 32-lead plcc ? 32-lead tsop (8mm x 14mm, 8mm x 20mm) ? 32-pin pdip all non-pb (lead-free) devices are rohs compliant product description the sst29ee/ve010 are 128k x8 cmos page-write eeproms manufactured with sst?s proprietary, high-per- formance cmos superflash technology. the split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. the sst29ee/ve010 write with a single power supply. internal erase/program is transparent to the user. the sst29ee/ve010 conform to jedec standard pinouts for byte-wide memories. featuring high performance page-write, the sst29ee/ ve010 provide a typical byte-write time of 39 sec. the entire memory, i.e., 128 kbyte, can be written page-by- page in as little as 5 seconds, when using interface features such as toggle bit or data# polling to indicate the comple- tion of a write cycle. to protect against inadvertent write, the sst29ee/ve010 have on-chip hardware and software data protection schemes. designed, manufactured, and tested for a wide spectrum of applications, the sst29ee/ ve010 are offered with a guaranteed page-write endur- ance of 10,000 cycles. data retention is rated at greater than 100 years. the sst29ee/ve010 are suited for applications that require convenient and economical updating of pro- gram, configuration, or data memory. for all system applications, the sst 29ee/ve010 significantly improve performance and reliability, while lowering power consumption. the sst29ee/ve010 improve flexibility while lowering the cost for program, data, and configuration storage applications. to meet high density, surface mount requirements, the sst29ee/ve010 are offered in 32-lead plcc and 32-lead tsop packages. a 600-mil, 32-pin pdip package is also available. see figures 1, 2, and 3 for pin assignments. device operation the sst page-write eeprom offers in-circuit electrical write capability. the sst29ee/ve010 does not require separate erase and program operations. the internally timed write cycle executes both erase and program trans- parently to the user. the sst29ee/ve010 have industry standard optional software data protection, which sst recommends always to be enabled. the sst29ee/ve010 are compatible with industry standard eeprom pinouts and functionality. sst29ee / ve0101mb (x8) page-write, small-sector flash memories
2 data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 ?2005 silicon storage technology, inc. s71061-11-000 9/05 read the read operations of the sst29ee/ve010 are con- trolled by ce# and oe#, both have to be low for the system to obtain data from the outputs. ce# is used for device selection. when ce# is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce# or oe# is high. refer to the read cycle timi ng diagram for further details (figure 4). write the page-write to the sst29ee/ve010 should always use the jedec standard software data protection (sdp) three-byte command sequence. the sst29ee/ve010 contain the optional jedec approved software data pro- tection scheme. sst recommends that sdp always be enabled, thus, the description of the write operations will be given using the sdp enabled format. the three-byte sdp enable and sdp write commands are identical; therefore, any time a sdp write command is issued, software data protection is automatically assured. the first time the three-byte sdp command is given, the device becomes sdp enabled. subsequent issuance of the same command bypasses the data protection for the page being written. at the end of the desired page-write, the entire device remains protected. for additional descriptions, please see the application notes, the proper use of jedec standard software data protection and protecting against unintentional writes when using single power supply flash memories . the write operation consists of three steps. step 1 is the three-byte load sequence for software data protection. step 2 is the byte-load cycle to a page buffer of the sst29ee/ve010. steps 1 and 2 use the same timing for both operations. step 3 is an internally controlled write cycle for writing the data loaded in the page buffer into the memory array for nonvolatile storage. during both the sdp three-byte load sequence and the byte-load cycle, the addresses are latched by the falling edge of either ce# or we#, whichever occurs last. the data is latched by the ris- ing edge of either ce# or we#, whichever occurs first. the internal write cycle is initiated by the t blco timer after the rising edge of we# or ce#, whichever occurs first. the write cycle, once initiated, w ill continue to completion, typi- cally within 5 ms. see figures 5 and 6 for we# and ce# controlled page-write cycle timing diagrams and figures 15 and 17 for flowcharts. the write operation has three functional cycles: the soft- ware data protection load sequence, the page-load cycle, and the internal write cycle. the software data protection consists of a specific three-byte load sequence that allows writing to the selected pag e and will leave the sst29ee/ ve010 protected at the end of the page-write. the page- load cycle consists of loading 1 to 128 bytes of data into the page buffer. the internal write cycle consists of the t blco time-out and the write timer operation. during the write operation, the only valid reads are data# polling and tog- gle bit. the page-write operation allows the loading of up to 128 bytes of data into the page buffer of the sst29ee/ve010 before the initiation of the in ternal write cycle. during the internal write cycle, all the data in the page buffer is written simultaneously into the memory array. hence, the page- write feature of sst29ee/ve010 allow the entire memory to be written in as little as 5 seconds. during the internal write cycle, the host is free to perform additional tasks, such as to fetch data from other locations in the system to set up the write to the next page. in each page-write oper- ation, all the bytes that are loaded into the page buffer must have the same page address, i.e. a 7 through a 16 . any byte not loaded with user data will be written to ffh. see figures 5 and 6 for the page-write cycle timing dia- grams. if after the completion of the three-byte sdp load sequence or the initial byte-load cycle, the host loads a sec- ond byte into the page buffer within a byte-load cycle time (t blc ) of 100 s, the sst29ee/ve010 will stay in the page-load cycle. additional bytes are then loaded consecu- tively. the page-load cycle will be terminated if no addi- tional byte is loaded into the page buffer within 200 s (t blco ) from the last byte-load cycle, i.e., no subsequent we# or ce# high-to-low transition after the last rising edge of we# or ce#. data in the page buffer can be changed by a subsequent byte-load cycle. the page-load period can continue indefinitely, as long as the host continues to load the device within the byte-load cycle time of 100 s. the page to be loaded is determined by the page address of the last byte loaded. software chip-erase the sst29ee/ve010 provide a chip-erase operation, which allows the user to simultaneously clear the entire memory array to the ?1? state. this is useful when the entire device must be quickly erased. the software chip-erase operation is initiated by using a specific six-byte load sequenc e. after the load sequence, the device enters into an internally timed cycle similar to the write cycle. during the erase operation, the only valid read is toggle bit. see table 4 for the load sequence, figure 10 for timing diagram, and figure 19 for the flowchart.
data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 3 ?2005 silicon storage technology, inc. s71061-11-000 9/05 write operation status detection the sst29ee/ve010 provide two software means to detect the completion of a write cycle, in order to optimize the system write cycle time. the software detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising we# or ce# whichever occurs first, which ini- tiates the internal write cycle. the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to con- flict with either dq 7 or dq 6 . in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejec- tion is valid. data# polling (dq 7 ) when the sst29ee/ve010 are in the internal write cycle, any attempt to read dq 7 of the last byte loaded during the byte-load cycle will receive the complement of the true data. once the write cycle is completed, dq 7 will show true data. note that even though dq 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be invalid: valid data on the entire dat a bus will appear in subsequent successive read cycles after an interval of 1 s. see fig- ure 7 for data# polling timing diagram and figure 16 for a flowchart. toggle bit (dq 6 ) during the internal write cycle, any consecutive attempts to read dq 6 will produce alternating ?0?s and ?1?s, i.e. toggling between 0 and 1. when the write cycle is completed, the toggling will stop. the device is then ready for the next operation. see figure 8 for toggle bit timing diagram and figure 16 for a flowchart. the initial read of the toggle bit will typically be a ?1?. data protection the sst29ee/ve010 provide both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 2.5v. write inhibit mode: forcing oe# low, ce# high, or we# high will inhibit the write oper ation. this prevents inadvert- ent writes during power-up or power-down. software data protection (sdp) the sst29ee/ve010 provide the jedec approved optional software data protection scheme for all data alter- ation operations, i.e., write and chip-erase. with this scheme, any write operation requires the inclusion of a series of three-byte load operations to precede the data loading operation. the three-byte load sequence is used to initiate the write cycle, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. the sst29ee/ve010 are shipped with the software data protection disabled. the software protection scheme can be enabled by apply- ing a three-byte sequence to the device, during a page- load cycle (figures 5 and 6). the device will then be auto- matically set into the data protect mode. any subsequent write operation will require the preceding three-byte sequence. see table 4 for the specific software command codes and figures 5 and 6 for the timing diagrams. to set the device into the unprotected mode, a six-byte sequence is required. see table 4 for the specific codes and figure 9 for the timing diagram. if a write is attempted while sdp is enabled the device will be in a non-accessible state for ~300 s. sst recommends software data protection always be enabled. see figure 17 for flowcharts. the sst29ee/ve010 software data protection is a global command, protecting all pages in the entire memory array once enabled. therefore using sdp for a single page- write will enable sdp for the entire array. single pages by themselves cannot be sdp enabled. single power supply reprogrammable nonvolatile memo- ries may be unintentionally altered. sst strongly recom- mends that software data protection (sdp) always be enabled. the sst29ee/ve010 should be programmed using the sdp command sequence.
4 data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 ?2005 silicon storage technology, inc. s71061-11-000 9/05 please refer to the following application notes for more information on using sdp: protecting against unintentional writes when using single power supply flash memories the proper use of jedec standard software data protection product identification the product identification mode identifies the device as the sst29ee/ve010 and manufacturer as sst. this mode is accessed via software. for details, see table 4, figure 11 for the software id entry and read timing diagram and figure 18, for the id entry com- mand sequence flowchart. product identification mode exit in order to return to the standard read mode, the software product identification mode must be exited. exiting is accomplished by issuing the software id exit (reset) opera- tion, which returns the device to the read operation. the reset operation may also be used to reset the device to the read mode after an inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. see table 4 for software command codes, figure 12 for timing waveform, and figure 18 for a flowchart. table 1: p roduct i dentification address data manufacturer?s id 0000h bfh device id sst29ee010 0001h 07h sst29ve010 0001h 08h t1.4 1061 y-decoder and page latches i/o buffers and data latches 1061 b1.0 address buffer & latches x-decoder dq 7 - dq 0 a 16 - a 0 we# oe# ce# superflash memory control logic f unctional b lock d iagram
data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 5 ?2005 silicon storage technology, inc. s71061-11-000 9/05 figure 1: p in a ssignments for 32- lead plcc figure 2: p in a ssignments for 32- lead tsop figure 3: p in a ssignments for 32- pin pdip 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a7 a6 a5 a4 a3 a2 a1 a0 d q0 a14 a13 a8 a9 a11 oe# a10 ce# dq7 4 3 2 1 32 31 30 a1 2 a1 5 a1 6 nc v d d we # nc 32-lead plcc top view 1061 32-plcc p01 .0 14 15 16 17 18 19 20 d q1 d q2 v ss d q3 d q4 d q5 d q6 a11 a9 a8 a13 a14 nc w e# v dd nc a16 a15 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1061 32-tsop f02 .0 standard pinout top view die up 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-pin pdip top view 1061 32-pdip p03.0 nc a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 d q0 d q1 d q2 v ss 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v d d we # nc a1 4 a1 3 a8 a9 a1 1 oe # a1 0 ce # dq 7 dq 6 dq 5 dq 4 dq 3
6 data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 ?2005 silicon storage technology, inc. s71061-11-000 9/05 table 2: p in d escription symbol pin name functions a 16 -a 7 row address inputs to provide memory addresses. row addresses define a page for a write cycle. a 6 -a 0 column address inputs column addresses are toggled to load page data dq 7 -dq 0 data input/output to output data during read cycles and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe# or ce# is high. ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers. we# write enable to control the write operations. v dd power supply to provide: 5.0v supply (4.5-5.5v) for sst29ee010 2.7v supply (2.7-3.6v) for sst29ve010 v ss ground nc no connection unconnected pins. t2.3 1061 table 3: o peration m odes s election mode ce# oe# we# dq address read v il v il v ih d out a in page-write v il v ih v il d in a in standby v ih x 1 1. x can be v il or v ih , but no other value. x high z x write inhibit x v il x high z/ d out x xxv ih high z/ d out x software chip-erase v il v ih v il d in a in, see table 4 product identification software mode v il v ih v il manufacturer?s id (bfh) device id 2 2. device id = 07h for sst29ee010 and 08h for sst29ve010 see table 4 sdp enable mode v il v ih v il see table 4 sdp disable mode v il v ih v il see table 4 t3.4 1061
data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 7 ?2005 silicon storage technology, inc. s71061-11-000 9/05 note: this product supports both the jedec st andard three-byte command code sequence and sst ?s original six-byte command code sequence. for new designs, sst recommends that the three-byte command code sequence be used. table 4: s oftware c ommand s equence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data addr 1 data addr 1 data addr 1 data addr 1 data addr 1 data software data protect enable & page-write 5555h aah 2aaah 55h 5555h a0h addr 2 data software chip-erase 3 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h software id entry 4,5 5555h aah 2aaah 55h 5555h 90h software id exit 5555h aah 2aaah 55h 5555h f0h alternate software id entry 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 60h t4.3 1061 1. address format a 14 -a 0 (hex), addresses a 15 and a 16 can be v il or v ih , but no other value. 2. page-write consists of loading up to 128 bytes (a 6 -a 0 ) 3. the software chip-erase function is not supported by the industrial temperature part. please contact sst if you require this f unction for an industrial temperature part. 4. the device does not remain in software product id mode if powered down. 5. with a 14 -a 1 = 0; sst manufacturer?s id = bfh, is read with a 0 = 0, sst29ee010 device id = 07h, is read with a 0 = 1 sst29ve010 device id = 08h, is read with a 0 = 1 6. alternate six-byte software product id command code
8 data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 ?2005 silicon storage technology, inc. s71061-11-000 9/05 absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v voltage on a 9 pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 14.0v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w through hole lead soldering temperature (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300c surface mount solder reflow temperature 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 m a 1. excluding certain with-pb 32-plcc units, all packages are 260 c capable in both non-pb and with-pb solder versions. certain with-pb 32-plcc package types are capable of 240 c for 10 seconds; please consult the factory for the latest information. 2. outputs shorted for no more than one second. no more than one output shorted at a time. o perating r ange for sst29ee010 range ambient temp v dd commercial 0c to +70c 4.5-5.5v industrial -40c to +85c 4.5-5.5v o perating r ange for sst29ve010 range ambient temp v dd commercial 0c to +70c 2.7-3.6v industrial -40c to +85c 2.7-3.6v ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . 10 ns output load . . . . . . . . . . . . . . . . . . . . . 1 ttl gate and c l = 100 pf see figures 13 and 14
data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 9 ?2005 silicon storage technology, inc. s71061-11-000 9/05 table 5: dc o perating c haracteristics v dd = 4.5-5.5v for sst29ee010 symbol parameter limits test conditions min max units i dd power supply current address input=v ilt /v iht, at f=1/t rc min, v dd =v dd max read 30 ma ce#=oe#=v il , we#=v ih , all i/os open program and erase 50 ma ce#=we#=v il , oe#=v ih , v dd =v dd max i sb1 standby v dd current (ttl input) 3 ma ce#=oe#=we#=v ih , v dd =v dd max i sb2 standby v dd current (cmos input) 50 a ce#=oe#=we#=v dd -0.3v, v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ih input high voltage 2.0 v v dd =v dd max v ol output low voltage 0.4 v i ol =2.1 ma, v dd =v dd min v oh output high voltage 2.4 v i oh =-400 a, v dd =v dd min t5.4 1061 table 6: dc o perating c haracteristics v dd = 2.7-3.0v for sst29ve010 symbol parameter limits test conditions min max units i dd power supply current address input=v ilt /v iht, at f=1/t rc min, v dd =v dd max read 12 ma ce#=oe#=v il , we#=v ih , all i/os open program and erase 15 ma ce#=we#=v il , oe#=v ih , v dd =v dd max i sb1 standby v dd current (ttl input) 1 ma ce#=oe#=we#=v ih , v dd =v dd max i sb2 standby v dd current (cmos input) 15 a ce#=oe#=we#=v dd -0.3v, v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ih input high voltage 2.0 v v dd =v dd max v ol output low voltage 0.4 v i ol =100 a, v dd =v dd min v oh output high voltage 2.4 v i oh =-100 a, v dd =v dd min t6.5 1061
10 data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 ?2005 silicon storage technology, inc. s71061-11-000 9/05 table 7: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read 1 power-up to read operation 100 s t pu-write 1 power-up to write operation 5 ms t7.1 1061 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. table 8: c apacitance (t a = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t8.0 1061 table 9: r eliability c haracteristics symbol parameter minimum spec ification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 ma jedec standard 78 t9.5 1061
data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 11 ?2005 silicon storage technology, inc. s71061-11-000 9/05 ac characteristics table 10: r ead c ycle t iming p arameters for sst29ee010 symbol parameter sst29ee010-70 sst29ee010-90 units min max min max t rc read cycle time 70 90 ns t ce chip enable access time 70 90 ns t aa address access time 70 90 ns t oe output enable access time 30 40 ns t clz 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. ce# low to active output 0 0 ns t olz 1 oe# low to active output 0 0 ns t chz 1 ce# high to high-z output 20 30 ns t ohz 1 oe# high to high-z output 20 30 ns t oh 1 output hold from address change 0 0 ns t10.2 1061 table 11: r ead c ycle t iming p arameters for sst29ve010 symbol parameter sst29ve010-150 sst29ve010-200 units min max min max t rc read cycle time 150 200 ns t ce chip enable access time 150 200 ns t aa address access time 150 200 ns t oe output enable access time 80 100 ns t clz 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. ce# low to active output 0 0 ns t olz 1 oe# low to active output 0 0 ns t chz 1 ce# high to high-z output 50 50 ns t ohz 1 oe# high to high-z output 50 50 ns t oh 1 output hold from address change 0 0 ns t11.2 1061
12 data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 ?2005 silicon storage technology, inc. s71061-11-000 9/05 table 12: p age -w rite c ycle t iming p arameters symbol parameter sst29ee010 sst29le/ve010 units min max min max t wc write cycle (erase and program) 10 10 ms t as address setup time 0 0 ns t ah address hold time 50 70 ns t cs we# and ce# setup time 0 0 ns t ch we# and ce# hold time 0 0 ns t oes oe# high setup time 0 0 ns t oeh oe# high hold time 0 0 ns t cp ce# pulse width 70 120 ns t wp we# pulse width 70 120 ns t ds data setup time 35 50 ns t dh 1 data hold time 0 0 ns t blc 1 byte load cycle time 0.05 100 0.05 100 s t blco 1 byte load cycle time 200 200 s t ida 1 software id access and exit time 10 10 s t sce software chip-erase 20 20 ms t12.5 1061 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er.
data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 13 ?2005 silicon storage technology, inc. s71061-11-000 9/05 figure 4: r ead c ycle t iming d iagram figure 5: we# c ontrolled p age -w rite c ycle t iming d iagram 1061 f04.0 ce# a ddress a 16-0 oe# we# dq 7-0 v ih t clz t oh data valid data valid t olz t oe high-z high-z t ce t chz t ohz t rc t aa 1061 f05.0 ce# oe# we# a ddress a 16-0 dq 7-0 sw0 aa 55 a0 data valid sw1 sw2 byte 0 byte 1 byte 127 t ds t dh t blc t blco t wc t wp t oeh t oes t ch t cs t ah t as 5555 three-byte sequence for enabling sdp 2aaa 5555
14 data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 ?2005 silicon storage technology, inc. s71061-11-000 9/05 figure 6: ce# c ontrolled p age -w rite c ycle t iming d iagram figure 7: d ata # p olling t iming d iagram 1061 f06.0 ce# oe# we# a ddress a 16-0 dq 7-0 sw0 aa 55 a0 data valid sw1 sw2 byte 0 byte 1 byte 127 t ds t dh t blc t blco t wc t cp t oeh t oes t ch t cs t ah t as 5555 three-byte sequence for enabling sdp 2aaa 5555 1061 f07.0 ce# oe# we# t wc + t blco d# t oe t oeh t ce t oes d# d a ddress a 16-0 dq 7 d
data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 15 ?2005 silicon storage technology, inc. s71061-11-000 9/05 figure 8: t oggle b it t iming d iagram figure 9: s oftware d ata p rotect d isable t iming d iagram 1061 f08.0 ce# oe# we# t wc + t blco two read cycles with same outputs t oeh t oe t oes t ce a ddress a 16-0 dq 6 1061 f09.0 ce# oe# we# a ddress a 14-0 dq 7-0 sw0 sw1 sw2 sw3 sw4 sw5 t blco t blc t wc t wp 5555 5555 55 aa 55 20 aa 80 six-byte sequence for disabling software data protection 2aaa 2aaa 5555 5555
16 data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 ?2005 silicon storage technology, inc. s71061-11-000 9/05 figure 10: s oftware c hip -e rase t iming d iagram figure 11: s oftware id e ntry and r ead 1061 f10.0 ce# oe# we# a ddress a 14-0 dq 7-0 sw0 sw1 sw2 sw3 sw4 sw5 t blco t blc t sce t wp 5555 5555 55 aa 55 10 aa 80 six-byte code for software chip-erase 2aaa 2aaa 5555 5555 1061 f11.1 ce# oe# we# a ddress a 14-0 dq 7-0 sw0 sw1 sw2 device id = 07h for sst29ee010 = 08h for sst29ve010 t ida t aa t blc t wp 5555 55 aa bf device id 90 three-byte sequence for software id entry 0000 2aaa 0001 5555
data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 17 ?2005 silicon storage technology, inc. s71061-11-000 9/05 figure 12: s oftware id e xit and r eset 1061 f12.0 ce# oe# we# a ddress a 14-0 dq 7-0 sw0 sw1 sw2 t ida t blc t wp 5555 55 aa f0 three-byte sequence for software id exit and reset 2aaa 5555
18 data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 ?2005 silicon storage technology, inc. s71061-11-000 9/05 figure 13: ac i nput /o utput r eference w aveforms figure 14: a t est l oad e xample 1061 f13.0 reference points output input v ht v lt v ht v lt v iht v ilt ac test inputs are driven at v iht (2.4v) for a logic ?1? and v ilt (0.4 v) for a logic ?0?. measurement reference points for inputs and outputs are v ht (2.0 v) and v lt (0.8 v). input rise and fall times (10% ? 90%) are <10 ns. note: v ht - v high te s t v lt - v low te s t v iht - v input high test v ilt - v input low test 1061 f14.0 to tester t o dut c l r l low r l hig h v dd
data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 19 ?2005 silicon storage technology, inc. s71061-11-000 9/05 figure 15: w rite a lgorithm 1061 f15 .0 no load byte data ye s byte address = 128? write completed increment byte address by 1 wait t blco wait for end of write (t wc , data# polling bit or toggle bit operation) set byte address = 0 set page address software data protect write command start see figure 17
20 data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 ?2005 silicon storage technology, inc. s71061-11-000 9/05 figure 16: w ait o ptions 1061 f16.0 no no read a byte from page ye s ye s does dq 6 match? write completed read same byte page-write initiated toggle bit wait t wc write completed page-write initiated internal timer read dq 7 (data for last byte loaded) is dq 7 = true data? write completed page-write initiated data# polling
da ta sh ee t 1 mbit p a g e -write eepr om sst29ee010 / sst29ve010 21 ? 2 00 5 s i l i c on st or ag e te chno l o g y , in c. s7 10 61- 1 1 - 0 0 0 9 / 05 figure 17 : s oftw ar e d ata p ro t e c t i o n f lo w c har ts 1061 f17.0 wr ite data: aah address: 5555h s oftware data pr otect enab le command sequence wr ite data: 55h address: 2aaah wr ite data: a0h address: 5555h w ait t wc w ait t blco sdp enab led load 0 to 128 bytes of page data optional p age load oper ation wr ite data: aah address: 5555h software data pr otect disab le command sequence wr ite data: 55h address: 2aaah wr ite data: 80h address: 5555h wr ite data: aah address: 5555h wa i t t wc wa i t t blco sdp disab led wr ite data: 55h address: 2aaah wr ite data: 20h address: 5555h
22 data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 ?2005 silicon storage technology, inc. s71061-11-000 9/05 figure 18: s oftware p roduct c ommand f lowcharts 1061 f18 .0 write data: aah address: 5555h s oftware product id entry command sequence write data: 55h address: 2aaah pause 10 s write data: 90h address: 5555h read software id write data: aah address: 5555h software product id exit & reset command sequence write data: 55h address: 2aaah pause 10 s write data: f0h address: 5555h return to normal operation
data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 23 ?2005 silicon storage technology, inc. s71061-11-000 9/05 figure 19: s oftware c hip -e rase c ommand c odes 1061 f19 .0 write data: aah address: 5555h s oftware chip-erase c ommand sequence write data: 55h address: 2aaah write data: aah address: 5555h write data: 55h address: 2aaah write data: 10h address: 5555h wait t sce chip-erase to ffh write data: 80h address: 5555h
24 data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 ?2005 silicon storage technology, inc. s71061-11-000 9/05 product ordering information environmental attribute e 1 = non-pb package modifier h = 32 leads or pins package type n = plcc e = tsop (type 1, die up, 8mm x 20mm) p = pdip w = tsop (type 1, die up, 8mm x 14mm) temperature range c = commercial = 0c to +70c i = industrial = -40c to +85c minimum endurance 4 = 10,000 cycles read access speed 200 = 200 ns 150 = 150 ns 90 = 90 ns 70 = 70 ns device density 010 = 1 mbit function e = page-write voltage e = 4.5-5.5v v = 2.7-3.6v product series 29 = page-write flash 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?. sst 29 xe 010 - 70 - 4c - nh e xx x x xxxx - xxx -xx - xxx x
data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 25 ?2005 silicon storage technology, inc. s71061-11-000 9/05 valid combinations for sst29ee010 sst29ee010-70-4c-nh sst29ee010-70-4c-wh sst29ee010-70-4c-eh sst29ee010-70-4c-ph sst29ee010-70-4c-nhe sst29ee010-70-4c-whe sst29ee010-70-4c-ehe sst29ee010-70-4c-phe sst29ee010-90-4c-nh sst29ee010-90-4c-wh sst29ee010-90-4c-eh sst29ee010-90-4c-ph sst29ee010-90-4c-nhe sst29ee010-90-4c-whe sst29ee010-90-4c-ehe sst29ee010-70-4i-nh sst29ee010-70-4i-wh sst29ee010-70-4i-eh sst29ee010-70-4i-nhe sst29ee010-70-4i-whe sst29ee010-70-4i-ehe valid combinations for sst29ve010 sst29ve010-150-4c-nh sst29ve010-1 50-4c-wh sst29ve010-150-4c-eh sst29ve010-150-4c-nhe sst29ve010-1 50-4c-whe sst29ve010-150-4c-ehe sst29ve010-200-4c-nh sst29ve010-2 00-4c-wh sst29ve010-200-4c-eh sst29ve010-200-4c-nhe sst29ve010-2 00-4c-whe sst29ve010-200-4c-ehe sst29ve010-150-4i-nh sst29ve010-1 50-4i-wh sst29ve010-150-4i-eh sst29ve010-150-4i-nhe sst29ve010-1 50-4i-whe sst29ve010-150-4i-ehe sst29ve010-200-4i-nh sst29ve010-2 00-4i-wh sst29ve010-200-4i-eh SST29VE010-200-4I-NHE sst29ve010-2 00-4i-whe sst29ve010-200-4i-ehe note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. note: the software chip-erase function is not supported by the industrial temperature part. please contact sst if this function is required in an industrial temperature part.
26 data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 ?2005 silicon storage technology, inc. s71061-11-000 9/05 packaging diagrams 32- lead p lastic l ead c hip c arrier (plcc) sst p ackage c ode : nh .040 .030 .021 .013 .530 .490 .095 .075 .140 .125 .032 .026 .032 .026 .029 .023 .453 .447 .553 .547 .595 .585 .495 .485 .112 .106 .042 .048 .048 .042 .015 min. top view side view bottom view 1 232 .400 bsc 32-plcc-nh- 3 n ote: 1. complies with jedec publication 95 ms-016 ae dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in inches (max/min). 3. dimensions do not include mold flash. maximum allowable mold flash is .008 inches. 4. coplanarity: 4 mils. .050 bsc .050 bsc optional pin #1 i dentifier .020 r. max. r. x 30?
data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 27 ?2005 silicon storage technology, inc. s71061-11-000 9/05 32- lead t hin s mall o utline p ackage (tsop) 8 mm x 14 mm sst p ackage c ode : wh 32-tsop-wh -7 n ote: 1. complies with jedec publication 95 mo-142 ba dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 1.20 max. 1mm pin # 1 identifier 12.50 12.30 14.20 13.80 0.70 0.50 8.10 7.90 0.27 0.17 0. 50 bsc 1.05 0.95 0.15 0.05 0.70 0.50 0?- 5? detail
28 data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 ?2005 silicon storage technology, inc. s71061-11-000 9/05 32- lead t hin s mall o utline p ackage (tsop) 8 mm x 20 mm sst p ackage c ode : eh 0.15 0.05 20.20 19.80 18.50 18.30 0.70 0.50 8.10 7.90 0.27 0.17 1.05 0.95 32-tsop-eh-7 n ote: 1.complies with jedec publication 95 mo-142 bd dimensions, although some dimensions may be more stringent. 2.all linear dimensions are in millimeters (max/min). 3.coplanarity: 0.1 mm 4.maximum allowable mold flash is 0.15 mm at the package ends, and 0.25mm between leads. pin # 1 identifier 0. 50 bsc 1mm 1.20 max. detail 0.70 0.50 0?- 5?
data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 29 ?2005 silicon storage technology, inc. s71061-11-000 9/05 32- pin p lastic d ual i n - line p ins (pdip) sst p ackage c ode : ph 32-pdip-ph-3 pin #1 identifier c l 32 1 base plane s eating plane note: 1. complies with jedec publication 95 mo-015 ap dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in inches (max/min). 3. dimensions do not include mold flash. maximum allowable mold flash is .010 inches. .200 .170 7? 4 plcs. .600 bsc .100 bsc .150 .120 .022 .016 .065 .045 .080 .070 .050 .015 .075 .065 1.655 1.645 .012 .008 0 ? 1 5? .625 .600 .550 .530
30 data sheet 1 mbit page-write eeprom sst29ee010 / sst29ve010 ?2005 silicon storage technology, inc. s71061-11-000 9/05 table 13: r evision h istory revision description date 07 2002 data book may 2002 08 removed 200 ns read access time for sst29le010 clarified i dd write to be program and erase in tables 5 and 6 on page 9 mar 2003 09 2004 data book added non-pb mpns and removed footnote (see page 25) nov 2003 10 added 150 ns mpns for sst29ve010 mar 2004 11 removed 3v device and associated mpns: refer to eol product data sheet s71061(01) added non-pb mpn for sst29ee010 pdip added rohs compliance information on page 1 and in the ?product ordering information? on page 24 updated the solder reflow temperature to the ?absolute maximum stress ratings? on page 8. sep 2005 silicon storage technology, inc. 1171 sonora court sunnyvale, ca 94086 telephone 408-735-9110 fax 408-735-9036 www.superflash.com or www.sst.com

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